Semiconductor differential amplifier circuit with feedback bias control

ABSTRACT

An input differential amplifier stage (10), which feeds an output stage (20), has a feedback loop originating at a node (N 1 ) in one branch, for controlling the current-source transistor (M 5 ) of that stage. The feedback loop is characterized by a direct connection to the gate electrode of a transistor (M 8 ) which drives the output stage (20), while the output at another node (N 2 ), in the other branch of the differential amplifier stage (10) is fed to another transistor (M 9 ) which also drives the output stage (20).

FIELD OF THE INVENTION

This invention relates to the field of semiconductor apparatus, and moreparticularly to MOS (metal-oxide-semiconductor) differential amplifiercircuits.

BACKGROUND OF THE INVENTION

It is known in the MOS art that semiconductor wafer-to-wafer processingvariations result in corresponding variations in the threshold voltagesof MOS transistors, particularly depletion mode load transistors. Thesevariations result in undesirable threshold voltage shifts from theproper value suitable for preserving the desired high incrementalresistance and these load transistors in the circuit.

In a typical input stage of an MOS amplifier circuit, a depletion loadtransistor is connected in series with an input driver transistor deviceand a current-source. Unless the threshold voltage of the loadtransistor is controlled with a precision sufficient to provide duringoperation the correct amount of voltage drop for a given current-source,the biasing of the input driver device in series with this loadtransistor will not be suitable for achieving the desired high gain andlinearity of the amplifier circuit. However, the correspondinglyrequired precision of processing control is difficult, if at allpossible, to achieve even in present day advanced processing technology.Moreover, variations in voltage supplies can also similarly deterioratethe gain of the amplifier.

In an application filed by Y. Tsividis (Ser. No. 010737) on Feb. 9,1979, now U.S. Pat. No. 4,213,098 an amplifier circuit in MOS technologywas described including a self-biased, stabilized differential amplifierstage that eliminated the need for precise matching of the thresholdvoltages of the depletion load transistors with the threshold voltagesof the current-source transistors; that is, the circuit operation wasrelatively insensitive to processing variations. On the other hand, thatcircuit required a relatively large number of extra transistors; therebythe circuit achieved the purposes of that invention, but at the expenseof a requirement of more silicon area.

SUMMARY OF THE INVENTION

Broadly speaking, this invention involves a differential amplifiercircuit stage, typically an input stage, in which both a current-sourcetransistor (M₅) and a first intermediate amplifier transistor (M₈) of adifferential amplifier input stage (10) are controlled by the samefeedback from a first node (N₁) located in one branch (M₁ in series withM₃) of the differential amplifier stage. The feedback pathadvantageously includes a pair of auxiliary transistors (M₆, M₇) whichalso provide D.C. bias for both the current-source transistor (M₅) andthe first intermediate amplifier transistor (M₈). In addition, acapacitor (C_(A)) is connected to the first node (N₁) to bypass from thefeedback path to ground (advantageously a source voltage supply terminalV_(SS)) any high frequency signals without disturbing the D.C. commonmode bias as stabilized by the feedback path; and at the same time thisbypass capacitor (C_(A)) improves the settling time of the amplifier inresponse to transient disturbances for relatively large (30 to 50 pf)capacitive loads, while it also improves the phase margin and gainmargin for all loads. By "high frequency signals" here is meant signalsof frequency in the neighborhood of f.sub.π, i.e., where the phase ofthe output relative to the input is equal to 180°. By "phase margin" ismeant (180°-φ₁), where φ₁ is the phase at unity gain of the outputrelative to the input. By "gain margin" is meant the gain at thatfrequency f.sub.π.

Accordingly, this invention involves a semiconductor amplifier circuitin MOS technology containing a differential amplifier input stage (10)including a pair of substantially identical first and second mutuallyparallel branches (M₁ M₃ and M₂ M₄), having respectively first andsecond output nodes (N₁, N₂), said branches being connected through acommon third node (N₃) to a controlled terminal of a commoncurrent-source transistor (M₅) for supplying current to both saidbranches, CHARACTERIZED IN THAT the first output node (N₁) of the firstbranch is connected to the gate electrode of a first auxiliarytransistor (M₆) having one of its controlled terminals connected to afeedback node (N_(F)) which is connected both to the gate electrode of afirst intermediate amplifier transistor (M₈) and to the gate electrodeof said current-source transistor (M₅). In a specific embodiment, thecircuit of the invention is CHARACTERIZED FURTHER BY a second auxiliarytransistor (M₇) one of whose controlled terminals and whose gateelectrode are connected to the feedback node (N_(F)), and the circuit isadvantageously also CHARACTERIZED FURTHER IN THAT the gate electrode ofsaid first auxiliary transistor (M₆) is connected through a bypasscapacitor (C_(A)) to a reference voltage source (ground). By "controlledterminal" is meant a relatively high current carrying terminal, as thedrain or source of an MOS transistor. With the circuit arrangement ofthis invention, fewer transistors are required in the input stage, andlower noise is obtainable, than in the circuit of the aforementionedpatent application of Y. Tsividis, but at some sacrifice ofinsensitivity of circuit performance to processing variations.

BRIEF DESCRIPTION OF THE DRAWING

This invention together with its advantages, objects, and features maybe better understood from the following detailed description when readin conjunction with the drawing in which:

FIG. 1 is a schematic circuit diagram of an amplifier in MOS technologycontaining a differential amplifier input stage in accordance with aspecific embodiment of the invention.

FIG. 2 is a schematic circuit diagram of the circuit shown in FIG. 1showing in greater detail the output stage of the circuit of FIG. 1.

The dashed lines across the channel of a given transistor indicates adepletion mode MOS transistor.

DETAILED DESCRIPTION

As shown in FIG. 1, an amplifier circuit 30 contains an MOS differentialamplifier input circuit stage 10 and an amplifier circuit output stage20. The input stage 10 includes a pair of signal input terminals 11 and12, and an output node N₄ which feeds the output stage 20. This outputstage 20 has an output terminal 13 for delivering to a utilization means(not shown) the output of the entire amplifier circuit 30 formed by theamplifier stages 10 and 20.

The input terminals 11 and 12 are connected to the gate electrodes ofMOS transistors M₁ and M₂, respectively. The sources of M₁ and M₂ areconnected together at a common node N₃ which is itself connected to thedrain of a current-source MOS transistor M₅. The source of M₅ isconnected to a source voltage supply terminal V_(SS), typically of about-5 volts (N-MOS technology). The drains of M₁ and M₂ are connected tothe nodes N₁ and N₂, respectively. These nodes N₁ and N₂ are separatelyconnected through MOS load transistors M₃ and M₄, respectively, to adrain voltage supply terminal V_(DD), typically supplying a voltage ofabout +5 volts (N-MOS technology). By "load transistor" is meant atransistor whose gate electrode is connected to a source or drain of thesame transistor. In addition, the node N₁ is connected through an inputstage feedback path (or "feedback loop") both to the gate electrode ofthe current-source transistor M₅ and to the gate electrode of a firstMOS intermediate amplifier transistor M₈. This input stage feedback pathruns from the first node N₁ to a feedback node N_(F), and this pathincludes a first auxiliary MOS transistors M₆ whose source-drain path isconnected in series with that of a second auxiliary MOS transistor M₇.More specifically, the node N₁ is connected to the gate electrode of thefirst auxiliary transistor M₆, while the source-drain paths of theauxiliary transistors M₆ and M₇ are connected together in series betweenthe drain and source terminals V_(DD) and V_(SS). A feedback node N_(F)between the source of M₆ and the drain of M₇ is connected to the gateelectrodes of M₅, M₇, and M₈.

The node N₂ is connected to the gate electrode of a second MOSintermediate amplifier transistor M₉ whose source-drain path isconnected in series with that of the first intermediate amplifiertransistor M₈. The transistors M₈ and M₉ serve as an intermediate bufferamplifier.

In order to curtail excess high frequency signals through the feedbackloop, the node N₁ is advantageously connected through a bypass capacitorC_(A) to a reference voltage terminal or ground, advantageously thesource voltage supply terminal V_(SS).

A node N₄ between the source-drain paths of the intermediate amplifiertransistors M₈ and M₉ serves as the output node of the intermediatebuffer amplifier formed by M₈ and M₉, and this node N₄ can be connectedto a variety of output amplifiers. For example, the node N₄ is connectedto the input terminal of an MOS inverting amplifier -A₂. This amplifier-A₂ typically comprises a cascode amplifier. An output node N₅ of thisamplifier -A₂ is connected to an input terminal of each of the MOSbuffer amplifiers A₁ and A₂. The amplifier A₁ functions as a bufferamplifier connected so as to deliver its output to the output terminal13 of the amplifier circuit 30, and the amplifier A₃ functions as anoutput feedback buffer amplifier connected so as to deliver its outputthrough a "compensation" capacitor C_(c) to the gate electrode of theload transistor M₉. The main purpose of this capacitor C_(c) is tocreate a dominant or single-pole in the response of the open loop gain,in order to provide low (unity) gain at frequencies corresponding tophase shifts of approximately 2π/3 (=120°) and thereby to suppressoscillations when the amplifier circuit 30 is connected in unity gainfeedback configurations.

The feedback capacitor C_(B) reduces the required value, and hence size,of the compensation capacitor C_(c) to a reasonable value consistentwith integrated MOS technology; that is, both C_(B) and C_(c) areadvantageously of sufficiently small required size so as to beconveniently fabricated as integrated circuit type of capacitors thatare commonly made in MOS technology, such as metal-polysilicon orpolysilicon-polysilicon capacitors, or MOS capacitors.

It should be noted that the load transistors M₃ and M₄ operate in thesaturation region, so that the current in each of these transistors isrelatively constant in response to relatively moderate changes in gatevoltages; whereas, the source-to-drain voltage drops across thesetransistors can change rather widely in response to such moderatechanges in gate voltages. Thus, these load transistors are characterizedby very high impedance, typically of the order of 10⁵ ohms or more; andeach of these load transistors may be replaced by an electrically linearresistive material, such as a polycrystalline silicon strip ofresistance of the order of 10⁵ to 10⁶ ohms.

During operation at relatively high frequencies (typically above about 1MHz) the portion of the input feedback path in the input stage 10 whichcontrols the gate electrode of the transistor M₈ tends to producedetrimental effects on gain and phase margin of the circuit 30 in theabsence of the bypass capacitor C_(A). More specifically, in the absenceof this bypass capacitor C_(A) the gain of the amplifier circuit 30 is,for reasonable values of C_(c), typically greater than unity atfrequencies for which the phase of the output relative to the input is180°; thereby, in the absence of C_(A) an instability is introduced bythe feedback from terminal 13 to terminal 11 in unity gain, or nearlyunity gain, configurations. The introduction of this bypass capacitorC_(A) reduces the gain at high frequencies for which the phase shift ofthe output relative to the C_(A) improves stability. Moreover, if C_(A)is sufficiently large, for example of the order of C_(c), the amplifier30 is characterized by a desirable single-pole response; that is, thecombined effect of the feedback from C_(c) to the gate electrode of M₉and the feedforward to the gate electrode of M₈ produces a 10dB drop ofpower gain per frequency decade in the neighborhood of the unity gainfrequency, which corresponds to the desired single-pole response atwhich the settling time for transients is minimized for both positiveand negative going signals applied to terminal 12 over a relatively widerange of loading at terminal 13. However, too large a value of C_(A)will cause excessively slow settling time and/or a settling time whichis undesirably dependent upon the polarity of the input signal appliedto terminal 12. Thus, the capacitor C_(A) substantially eliminatesexcess high frequency signals in the feedback loop from N₁ to N₄ andhence suppresses undesirable oscillation.

FIG. 2 shows a differential amplifier circuit 50, showing in greaterdetail a specific circuit realization 40 of the output stage 20 (FIG. 1)of the amplifier. Elements in the circuits shown in FIGS. 1 and 2 whichare identical are denoted with the same reference numerals. The outputcircuit stage 40 includes an MOS driver transistor M₁₀ which controlsthe cascode amplifier arrangement formed by depletion mode MOStransistors M₁₁, M₁₂, and M₁₃. These transistors M₁₁, M₁₂, and M₁₃,together with the transistor driver M₁₀, form a specific realization ofthe inverting amplifier -A₂ of FIG. 1 with output node N₅. A pair ofdepletion mode series connected MOS transistors M₁₄ and M₁₅ form abuffer amplifier in a source-follower configuration (equivalent to theamplifier A₃ of FIG. 1) which is connected to deliver its output throughthe compensation capacitor C_(c) to the node N₂. Another pair ofdepletion mode series connected MOS transistors M₁₆ and M₁₇ form anotherbuffer amplifier in a source-follower configuration (equivalent to theamplifier A₁ of FIG. 1) having an output terminal 13 serving as theoutput terminal for the entire amplifier circuit 50.

Suitable values for the parameters of the various components shown inthe circuit 40 may be illustratively selected (approximately) asfollows. The capacitance of C_(A) is 1.2 picofarad; the capacitance ofC_(B) is 0.8 picofarad; and the capacitance of C_(c) is 1.6 picofarad.The substrate, that is, the semiconductor body material in which thevarious capacitor and transistor devices typically are integrated, inN-MOS technology is substantially uniform P-type monocrystalline siliconof bulk resistivity typically in the range of 6 to 10 ohm-cm. Thedepletion mode transistors are formed typically by arsenic ionimplantation so that the threshold voltage of these depletion modetransistors (M₃, M₄, M₁₁, M₁₂, M₁₃, M₁₄, M₁₅, M₁₆, M₁₇) is typicallyabout -2.8 volts, while the threshold of the remaining, enhancement modetransistors (M₁, M₂, M₅, M₆, M₇, M₈, M₉, M₁₀) is typically about +0.25volts, all thresholds as measured under zero source-to-substrate biasvoltage. Because of processing variations, however, the thresholdvoltage may vary from semiconductor wafer-to-wafer substrate but issubstantially the same on a given wafer. The values of channelwidth/length (W/L), as well as operating drain-source currents (I_(D))and transconductances g_(m), are illustratively selected to beapproximately as follows:

    ______________________________________                                        W(μm)/L(μm)  I.sub.D (μA)                                                                       g.sub.m (μmho)                                  ______________________________________                                        M.sub.1                                                                              160/20          16      96.4                                           M.sub.2                                                                              160/20          16      96.4                                           M.sub.3                                                                              21/50           16      20.4                                           M.sub.4                                                                              21/50           16      20.4                                           M.sub.5                                                                              20/20           32      45.0                                           M.sub.6                                                                               8/80           37      14.4                                           M.sub.7                                                                              24/20           37      53.0                                           M.sub.8                                                                              24/20           37      53.0                                           M.sub.9                                                                               8/80           37      14.4                                           M.sub.10                                                                             24/8            112     152                                            M.sub.11                                                                             25.5/20         109     89.5                                           M.sub.12                                                                             16/8            3       89.5                                           M.sub.13                                                                              8/160          3       2.8                                            M.sub.14                                                                              8/14           69.5    45.1                                           M.sub.15                                                                             40/8            69.5    155.0                                          M.sub.16                                                                              8/14           69.5    45.1                                           M.sub.17                                                                             8/8             69.5    64.3                                           ______________________________________                                    

Although the invention has been described in detail in conjunction witha specific embodiment, various modifications can be made withoutdeparting from the scope of the invention. For example, P-MOS technologycan be used instead of N-MOS; other and different voltage supplies canbe used; and depletion mode transistors can replace enhancement modetransistors. Also, particularly if M₄ is an enhancement mode rather thandepletion mode transistor, the capacitor C_(c) may be advantageouslyconnected to the node N₄ instead of to the gate electrode of M₉.Moreover, other types of intermediate and output amplifier stages canalso be used than described above.

We claim:
 1. Semiconductor apparatus in MOS technology comprising adifferential amplifier input stage (10) including a pair ofsubstantially identical first and second mutually parallel branches (M₁M₃ and M₂ M₄) having, respectively, first and second output nodes (N₁,N₂), said branches being connected through a common third node (N₃) to acontrolled terminal of a common current-source transistor (M₅) forsupplying current to both said branches, CHARACTERIZED IN THAT the firstoutput node (N₁) of the first branch is directly connected to the gateelectrode of a first auxiliary transistor (M₆) having one of itscontrolled terminals connected to a feedback node (N_(F)) which isconnected both to the gate electrode of a first intermediate amplifiertransistor (M₈) and to the gate electrode of said current-sourcetransistor (M₅).
 2. Apparatus according to claim 1 CHARACTERIZED FURTHERBY a second auxiliary transistor (M₇) one of whose controlled terminalsand whose gate electrode are connected to the feedback node (N_(F)). 3.Apparatus according to claim 1 or 2, CHARACTERIZED FURTHER IN THAT thegate electrode of said first auxiliary transistor (M₆) is connectedthrough a bypass capacitor (C_(A)) to a reference voltage terminal(ground).
 4. Semiconductor apparatus according to claim 3 in which thefirst branch and the second branch, respectively, includes a first and asecond input signal transistor (M₁, M₂) one of the gate terminals ofeach of which is connected, respectively, to a separate input signalterminal (11, 12).
 5. Semiconductor apparatus according to claim 4 inwhich each said branch further includes a separate electrical loaddevice (M₃, M₄) each of which is connected in series with thesource-drain path of the corresponding input signal transistor (M₁, M₂),the first and the second node (N₁, N₂) being located, respectively,between the source-drain path of the input signal transistor (M₁, M₂)and that of the corresponding load (M₃, M₄) in the first and secondbranch, respectively.
 6. Semiconductor apparatus according to claim 4 inwhich the source-drain path of the first intermediate amplifiertransistor (M₈) is connected in series with that of a secondintermediate amplifier transistor (M₉).
 7. Semiconductor apparatusaccording to claim 6 in which a fourth node (N₄) between thesource-drain paths of the first and second intermediate amplifiertransistors (M₈, M₉) is connected to the input terminal of an invertingamplifier (-A₂).
 8. Semiconductor apparatus according to claim 7 inwhich an output node (N₅) of the said inverting amplifier (-A₂) isconnected through a buffer amplifier (A₃) in series with a compensatingcapacitor (C_(c)) to the second node (N₂).
 9. Semiconductor apparatusaccording to claim 5 in which each said load device is an MOS transistorwhose gate electrode is connected to its source.
 10. A differentialamplifier stage (10) which comprises:(a) a first input MOS transistor(M₁) whose source-drain path is connected in series with that of a thirdMOS transistor (M₃), thereby forming a first node (N₁) between theirrespective source-drain paths; (b) a second input MOS transistor (M₂)whose source-drain path is connected in series with that of a fourth MOStransistor (M₄), thereby forming a second node (N₂) between theirrespective source-drain paths; (c) a current-source MOS transistor (M₅)whose source-drain path is connected to a third node (N₃) to which thesource-drain paths of the first and second transistors (M₁, M₂) areconnected in common; (d) a feedback loop from said first node (N₁) to afeedback node (N_(F)) connected to the gate electrode of thecurrent-source transistor (M₅), said feedback loop including a firstauxiliary transistor (M₆) having one of its controlled terminalsconnected to the feedback node (N_(F)) and having its gate electrodedirectly connected to the first node (N₁); (e) a first intermediateamplifier MOS transistor (M₈) whose gate electrode is connected to thefeedback node (N_(F)).
 11. An amplifier stage according to claim 10 inwhich said feedback loop includes a bypass capacitor (C_(A)) connectedbetween the first node (N₁) and a reference voltage terminal (ground).12. An amplifier stage according to claim 11 in which said feedback loopfurther includes a second auxiliary transistor (M₇) one of whosecontrolled terminals and whose gate electrode are connected to thefeedback node (N_(F)).
 13. An amplifier stage according to claim 11 or12 in which the source-drain path of the first intermediate amplifiertransistor (M₈) is connected in series with that of a secondintermediate amplifier transistor (M₉).